1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a structure of a transistor using a metallic oxide film as a gate insulating film and a method for manufacturing the same.
2. Description of the Related Art
Finer processing of a MOS transistor seems to have no bounds, and a gate length of 0.1 .mu.m will become a reality in the near future. This finer processing increases the speed of a device and reduces the power consumption and the area of the device. Also in recent years, this finer processing enables many devices to be mounted on the same chip area and hence can realize a multi-function LSI.
It is thought, however, that the pursuit of the finer processing runs into big barriers at a gate length of 0.1 .mu.m. One of the barriers is the limit of thinning of a gate oxide film. A conventional gate insulating film uses SiO.sub.2 because SiO.sub.2 can satisfy two characteristics indispensable to the action of the device, that is, the SiO.sub.2 includes few fixed electric charges and hardly forms an interface level at the interface between the gate insulating film and the Si of a channel portion. Also, since SiO.sub.2 can form a thin film simply with good controllability, it is also effective in the finer processing of the device. However, the relative dielectric constant of the SiO.sub.2 is small (3.9) and hence the SiO.sub.2 film is made less than 3 nanometers thick so as to satisfy the performance of the transistor in the generation of a gate length of 0.1 .mu.m or less. It is predicted that this thin film thickness presents a problem that carriers directly tunnel through the film and increase the leakage current between the gate and the substrate.
Therefore, research aimed at forming a thick gate insulating film and at preventing a tunneling phenomenon has been conducted by using a material having a larger relative dielectric constant than SiO.sub.2. A metallic oxide film made of Ta.sub.2 O.sub.5 or TiO.sub.2 is used as a material having a large relative dielectric constant. It is thought that these are promising materials for preventing the tunneling phenomenon because they have a large relative dielectric constant of about 20 or 90 and hence the thickness thereof can be made about 5 to 20 times as large as the thickness of the SiO.sub.2 in order to produce the same gate capacitance.
However, a problem has been pointed out that when a metallic oxide film is formed on a Si substrate by the use of a usual process flow, a Si oxide film having a low dielectric constant is formed with a thickness of about 1 nanometer to 2 nanometers between the metallic oxide film and the Si substrate by a heat treatment in each process. As a heat treatment after the formation of the metallic oxide film, there is an annealing treatment for activating impurities in source/drain regions after the formation of gate side walls (typically, annealing at 800.degree. C. for 60 minutes in a nitrogen atmosphere), an oxidizing process after forming a gate electrode (about 700.degree. C. to 900.degree. C.), a heating process when the gate side wall is deposited (about 600.degree. C. to 800.degree. C.), a heating process for densifying a highly dielectric film (about 600.degree. C. to 1000.degree. C.), and a sintering process (about 300.degree. C. to 500.degree. C.).
The Si oxide film formed by the heat treatment after the formation of the metallic oxide film has a small relative dielectric constant; therefore, it reduces the capacitance of the gate and the substrate and hence reduces the driving force of a MOS transistor. Also, a transistor having a short gate length markedly produces "a short channel effect" of reducing a gate voltage threshold for turning on.
As described above, in a case where a metallic oxide film having a high dielectric constant is used as a gate insulating film, there is a problem that a Si oxide film having a low dielectric constant is formed between the metallic oxide film and a Si substrate by a heat treatment performed after the formation of the metallic oxide film. This reduces the capacitance of the gate and the substrate and hence reduces the driving force of a MOS transistor. Also, a transistor having a short gate length presents a problem that it markedly produces "a short channel effect" of reducing a gate voltage threshold for turning on.